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[Author] Hiroaki KUNIEDA(45hit)

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  • A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector

    Gijun IDEI  Hiroaki KUNIEDA  

     
    PAPER

      Vol:
    E87-C No:6
      Page(s):
    956-963

    An adaptive 4-state phase-frequency detector (PFD) for clock and data recovery (CDR) PLL of non return to zero (NRZ) data is presented. The PLL achieves false-lock free operation with rapid frequency-capture and wide bit-rate-capture range. The variable bit rate operation is achieved by adaptive delay control of data delay. Circuitry and overall architecture are described in detail. A z-Domain analysis is also presented.

  • HOG-Based Object Detection Processor Design Using ASIP Methodology

    Shanlin XIAO  Tsuyoshi ISSHIKI  Dongju LI  Hiroaki KUNIEDA  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E100-A No:12
      Page(s):
    2972-2984

    Object detection is an essential and expensive process in many computer vision systems. Standard off-the-shelf embedded processors are hard to achieve performance-power balance for implementation of object detection applications. In this work, we explore an Application Specific Instruction set Processor (ASIP) for object detection using Histogram of Oriented Gradients (HOG) feature. Algorithm simplifications are adopted to reduce memory bandwidth requirements and mathematical complexity without losing reliability. Also, parallel histogram generation and on-the-fly Support Vector Machine (SVM) calculation architecture are employed to reduce the necessary cycle counts. The HOG algorithm on the proposed ASIP was accelerated by a factor of 63x compared to the pure software implementation. The ASIP was synthesized for a standard 90nm CMOS library, with a silicon area of 1.31mm2 and 47.8mW power consumption at a 200MHz frequency. Our object detection processor can achieve 42 frames-per-second (fps) on VGA video. The evaluation and implementation results show that the proposed ASIP is both area-efficient and power-efficient while being competitive with commercial CPUs/DSPs. Furthermore, our ASIP exhibits comparable performance even with hard-wire designs.

  • RHINE: Reconfigurable Multiprocessor System for Video CODEC

    Yoshinori TAKEUCHI  Zhao-Chen HUANG  Masatomo SAEKI  Hiroaki KUNIEDA  

     
    PAPER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    947-956

    This paper introduces the new application specific architecture RHINE (Reconfigurable Hierarchical Image Neo-multiprocessor Engine) that is a multiprocessor system for moving picture CODEC. The array processor is known to be originally suited for data parallel processing such as image signal processing which requires vast amount of computations and has the identical instruction sequences on data. However, the moving picture CODEC algorithm suffers from the large load imbalance in the processings on multi-processors with the separated sub-images. Some load balancing techniques are indispensable in such applications for the highest speed-up. RHINE gives one of the optimal solutions for such a load balancing due to its feature of the self reconfigurable architecture. RHINE consists of Block Processing Units (BPU) hierarchically, in each of which has a common bus architecture of multiprocessors with a block memory. Processors in a BPU move to the other BPU according to the load imbalance between BPUs by switching the bus connection between BPUs. The advantage of RHINE architecture is demonstrated by showing performance simulations for real moving pictures.

  • Orientation Field Estimation for Embedded Fingerprint Authentication System

    Wei TANG  Dongju LI  Tsuyoshi ISSHIKI  Hiroaki KUNIEDA  

     
    PAPER-Pattern Recognition

      Vol:
    E93-D No:7
      Page(s):
    1918-1926

    Orientation field (OF) estimation is a fundamental process in fingerprint authentication systems. In this paper, a novel binary pattern based low-cost OF estimation algorithm is proposed. The new method consists of two modules. The first is block-level orientation estimation and averaging in vector space by pixel level orientation statistics. The second is orientation quantization and smoothing. In the second module, the continuous orientation is quantized into fixed orientations with sufficient resolution (interval between fixed orientations). An effective smoothing scheme on the quantized orientation space is also proposed. The proposed algorithm is capable of stably processing poor-quality fingerprint images and is validated by tests conducted on an adaptive OF matching scheme. The proposed algorithm is also implemented into a fingerprint System on Chip (SoC) to comfirm that it satisfies the strict requirements of embedded system.

  • Unique Fingerprint-Image-Generation Algorithm for Line Sensors

    Hao NI  Dongju LI  Tsuyoshi ISSHIKI  Hiroaki KUNIEDA  

     
    PAPER-Image

      Vol:
    E94-A No:2
      Page(s):
    781-788

    It is theoretically impossible to restore the original fingerprint image from a sequence of line images captured by a line sensor. However, in this paper we propose a unique fingerprint-image-generation algorithm, which derives fingerprint images from sequences of line images captured at different swipe speeds by the line sensor. A continuous image representation, called trajectory, is used in modeling distortion of raw fingerprint images. Sequences of line images captured from the same finger are considered as sequences of points, which are sampled on the same trajectory in N-dimensional vector space. The key point here is not to reconstruct the original image, but to generate identical images from the trajectory, which are independent of the swipe speed of the finger. The method for applying the algorithm in a practical application is also presented. Experimental results on a raw fingerprint image database from a line sensor show that the generated fingerprint images are independent of swipe speed, and can achieve remarkable matching performance with a conventional minutiae matcher.

41-45hit(45hit)